// **************************************************************
// COPYRIGHT(c)2020, Xidian University
// All rights reserved.
//
// IP LIB INDEX : 
// IP Name      : 
//                
// File name    :
// Module name  : 
// Full name    :
//
// Author       :  Hbing 
// Email        :  2629029232@qq.com
// Data         :  2020/8/24
// Version      :  V 1.0 
// 
//Abstract      :
// Called by    :  Father Module
// 
// Modification history
// ------------------------------------------------------------------------------------------------------
// 
//  
// *********************************************************************
// `include "top_define.v"
// *******************
// *******************
// DESCRIPTION
// *******************
// 将宽度32深度33的ram改为寄存器，加快查找速率
// TIMESCALE
// ******************* 
`timescale 1ns/1ps 


module queue_infor_length_w16_d33_reg(
input  wire            clk       , // input clka
input  wire            wea       , // input  [0 : 0] wea
input  wire [5 : 0]    addra     , // input  [5 : 0] addra
input  wire [15: 0]    dina      , // input  [16: 0] dina
output reg  [15: 0]    douta     , // output [16: 0] douta
input  wire            rst_n     , // input rst_n
input  wire            web       , // input  [0 : 0] web
input  wire [5 : 0]    addrb     , // input  [5 : 0] addrb
input  wire [15: 0]    dinb      , // input  [16 : 0] dinb
output reg  [15: 0]    doutb     
 );
reg [15:0]      queue_infor_reg_0 ;
reg [15:0]      queue_infor_reg_1 ;
reg [15:0]      queue_infor_reg_2 ;
reg [15:0]      queue_infor_reg_3 ;
reg [15:0]      queue_infor_reg_4 ;
reg [15:0]      queue_infor_reg_5 ;
reg [15:0]      queue_infor_reg_6 ;
reg [15:0]      queue_infor_reg_7 ;
reg [15:0]      queue_infor_reg_8 ; 
reg [15:0]      queue_infor_reg_9 ;
reg [15:0]      queue_infor_reg_10;
reg [15:0]      queue_infor_reg_11;
reg [15:0]      queue_infor_reg_12;
reg [15:0]      queue_infor_reg_13;
reg [15:0]      queue_infor_reg_14;
reg [15:0]      queue_infor_reg_15;
reg [15:0]      queue_infor_reg_16;
reg [15:0]      queue_infor_reg_17;
reg [15:0]      queue_infor_reg_18;
reg [15:0]      queue_infor_reg_19;
reg [15:0]      queue_infor_reg_20;
reg [15:0]      queue_infor_reg_21;
reg [15:0]      queue_infor_reg_22;
reg [15:0]      queue_infor_reg_23;
reg [15:0]      queue_infor_reg_24;
reg [15:0]      queue_infor_reg_25;
reg [15:0]      queue_infor_reg_26;
reg [15:0]      queue_infor_reg_27;
reg [15:0]      queue_infor_reg_28;
reg [15:0]      queue_infor_reg_29;
reg [15:0]      queue_infor_reg_30;
reg [15:0]      queue_infor_reg_31;
reg [15:0]      queue_infor_reg_32;


//输出
always @(posedge clk or negedge rst_n) begin
    if(~rst_n) begin
        douta <= 16'd0;
    end
    else if (wea) begin
        douta <= douta;
    end
    else begin
        case (addra)
        6'd0  : begin
            douta <= queue_infor_reg_0 ;
        end 
        6'd1  : begin 
            douta <= queue_infor_reg_1 ;
        end 
        6'd2  : begin 
            douta <= queue_infor_reg_2 ;
        end 
        6'd3  : begin 
            douta <= queue_infor_reg_3 ;
        end 
        6'd4  : begin 
            douta <= queue_infor_reg_4 ;
        end 
        6'd5  : begin 
            douta <= queue_infor_reg_5 ;
        end 
        6'd6  : begin 
            douta <= queue_infor_reg_6 ;
        end 
        6'd7  : begin 
            douta <= queue_infor_reg_7 ;
        end 
        6'd8  : begin 
            douta <= queue_infor_reg_8 ;
        end 
        6'd9  : begin 
            douta <= queue_infor_reg_9 ;
        end 
        6'd10 : begin 
            douta <= queue_infor_reg_10;
        end 
        6'd11 : begin
            douta <= queue_infor_reg_11;
        end
        6'd12 : begin
            douta <= queue_infor_reg_12;
        end
        6'd13 : begin
            douta <= queue_infor_reg_13;
        end
        6'd14 : begin
            douta <= queue_infor_reg_14;
        end
        6'd15 : begin
            douta <= queue_infor_reg_15;
        end
        6'd16 : begin
            douta <= queue_infor_reg_16;
        end
        6'd17 : begin
            douta <= queue_infor_reg_17;
        end
        6'd18 : begin
            douta <= queue_infor_reg_18;
        end
        6'd19 : begin
            douta <= queue_infor_reg_19;
        end
        6'd20 : begin
            douta <= queue_infor_reg_20;
        end
        6'd21 : begin
            douta <= queue_infor_reg_21;
        end
        6'd22 : begin
            douta <= queue_infor_reg_22;
        end
        6'd23 : begin
            douta <= queue_infor_reg_23;
        end
        6'd24 : begin
            douta <= queue_infor_reg_24;
        end
        6'd25 : begin
            douta <= queue_infor_reg_25;
        end
        6'd26 : begin
            douta <= queue_infor_reg_26;
        end
        6'd27 : begin
            douta <= queue_infor_reg_27;
        end
        6'd28 : begin
            douta <= queue_infor_reg_28;
        end
        6'd29 : begin
            douta <= queue_infor_reg_29;
        end
        6'd30 : begin
            douta <= queue_infor_reg_30;
        end
        6'd31 : begin
            douta <= queue_infor_reg_31;
        end
        6'd32 : begin
            douta <= queue_infor_reg_32;
        end
        default: begin
            douta <= 16'd0;
        end
        endcase
    end
end

always @(posedge clk or negedge rst_n) begin
    if(~rst_n) begin
        doutb <= 16'd0;
    end
    else if (web) begin
        doutb <= doutb;
    end
    else begin
        case (addrb)
        6'd0  : begin
            doutb <= queue_infor_reg_0 ;
        end 
        6'd1  : begin 
            doutb <= queue_infor_reg_1 ;
        end 
        6'd2  : begin 
            doutb <= queue_infor_reg_2 ;
        end 
        6'd3  : begin 
            doutb <= queue_infor_reg_3 ;
        end 
        6'd4  : begin 
            doutb <= queue_infor_reg_4 ;
        end 
        6'd5  : begin 
            doutb <= queue_infor_reg_5 ;
        end 
        6'd6  : begin 
            doutb <= queue_infor_reg_6 ;
        end 
        6'd7  : begin 
            doutb <= queue_infor_reg_7 ;
        end 
        6'd8  : begin 
            doutb <= queue_infor_reg_8 ;
        end 
        6'd9  : begin 
            doutb <= queue_infor_reg_9 ;
        end 
        6'd10 : begin 
            doutb <= queue_infor_reg_10;
        end 
        6'd11 : begin
            doutb <= queue_infor_reg_11;
        end
        6'd12 : begin
            doutb <= queue_infor_reg_12;
        end
        6'd13 : begin
            doutb <= queue_infor_reg_13;
        end
        6'd14 : begin
            doutb <= queue_infor_reg_14;
        end
        6'd15 : begin
            doutb <= queue_infor_reg_15;
        end
        6'd16 : begin
            doutb <= queue_infor_reg_16;
        end
        6'd17 : begin
            doutb <= queue_infor_reg_17;
        end
        6'd18 : begin
            doutb <= queue_infor_reg_18;
        end
        6'd19 : begin
            doutb <= queue_infor_reg_19;
        end
        6'd20 : begin
            doutb <= queue_infor_reg_20;
        end
        6'd21 : begin
            doutb <= queue_infor_reg_21;
        end
        6'd22 : begin
            doutb <= queue_infor_reg_22;
        end
        6'd23 : begin
            doutb <= queue_infor_reg_23;
        end
        6'd24 : begin
            doutb <= queue_infor_reg_24;
        end
        6'd25 : begin
            doutb <= queue_infor_reg_25;
        end
        6'd26 : begin
            doutb <= queue_infor_reg_26;
        end
        6'd27 : begin
            doutb <= queue_infor_reg_27;
        end
        6'd28 : begin
            doutb <= queue_infor_reg_28;
        end
        6'd29 : begin
            doutb <= queue_infor_reg_29;
        end
        6'd30 : begin
            doutb <= queue_infor_reg_30;
        end
        6'd31 : begin
            doutb <= queue_infor_reg_31;
        end
        6'd32 : begin
            doutb <= queue_infor_reg_32;
        end
        default: begin
            doutb <= 16'd0;
        end
        endcase
    end
end

//reg 信息维护
always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        queue_infor_reg_0 <= 16'b0;
    end
    else if ((addra == 6'd0) && wea && (addrb == 6'd0) && web) begin
        queue_infor_reg_0 <= dina + dinb - queue_infor_reg_0;
    end
    else if ((addra == 6'd0) && wea) begin
        queue_infor_reg_0 <= dina;
    end
    else if((addrb == 6'd0) && web) begin
        queue_infor_reg_0 <= dinb;
    end
    else begin
        queue_infor_reg_0 <= queue_infor_reg_0;
    end
end

always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        queue_infor_reg_1 <= 16'b0;
    end
    else if ((addra == 6'd1) && wea && (addrb == 6'd1) && web) begin
        queue_infor_reg_1 <= dina + dinb - queue_infor_reg_1;
    end
    else if ((addra == 6'd1) && wea) begin
        queue_infor_reg_1 <= dina;
    end
    else if((addrb == 6'd1) && web) begin
        queue_infor_reg_1 <= dinb;
    end
    else begin
        queue_infor_reg_1 <= queue_infor_reg_1;
    end
end

always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        queue_infor_reg_2 <= 16'b0;
    end
    else if ((addra == 6'd2) && wea && (addrb == 6'd2) && web) begin
        queue_infor_reg_2 <= dina + dinb - queue_infor_reg_2;
    end
    else if ((addra == 6'd2) && wea) begin
        queue_infor_reg_2 <= dina;
    end
    else if((addrb == 6'd2) && web) begin
        queue_infor_reg_2 <= dinb;
    end
    else begin
        queue_infor_reg_2 <= queue_infor_reg_2;
    end
end

always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        queue_infor_reg_3 <= 16'b0;
    end
    else if ((addra == 6'd3) && wea && (addrb == 6'd3) && web) begin
        queue_infor_reg_3 <= dina + dinb - queue_infor_reg_3;
    end
    else if ((addra == 6'd3) && wea) begin
        queue_infor_reg_3 <= dina;
    end
    else if((addrb == 6'd3) && web) begin
        queue_infor_reg_3 <= dinb;
    end
    else begin
        queue_infor_reg_3 <= queue_infor_reg_3;
    end
end

always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        queue_infor_reg_4 <= 16'b0;
    end
    else if ((addra == 6'd4) && wea && (addrb == 6'd4) && web) begin
        queue_infor_reg_4 <= dina + dinb - queue_infor_reg_4;
    end
    else if ((addra == 6'd4) && wea) begin
        queue_infor_reg_4 <= dina;
    end
    else if((addrb == 6'd4) && web) begin
        queue_infor_reg_4 <= dinb;
    end
    else begin
        queue_infor_reg_4 <= queue_infor_reg_4;
    end
end

always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        queue_infor_reg_5 <= 16'b0;
    end
    else if ((addra == 6'd5) && wea && (addrb == 6'd5) && web) begin
        queue_infor_reg_5 <= dina + dinb - queue_infor_reg_5;
    end
    else if ((addra == 6'd5) && wea) begin
        queue_infor_reg_5 <= dina;
    end
    else if((addrb == 6'd5) && web) begin
        queue_infor_reg_5 <= dinb;
    end
    else begin
        queue_infor_reg_5 <= queue_infor_reg_5;
    end
end

always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        queue_infor_reg_6 <= 16'b0;
    end
    else if ((addra == 6'd6) && wea && (addrb == 6'd6) && web) begin
        queue_infor_reg_6 <= dina + dinb - queue_infor_reg_6;
    end
    else if ((addra == 6'd6) && wea) begin
        queue_infor_reg_6 <= dina;
    end
    else if((addrb == 6'd6) && web) begin
        queue_infor_reg_6 <= dinb;
    end
    else begin
        queue_infor_reg_6 <= queue_infor_reg_6;
    end
end

always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        queue_infor_reg_7 <= 16'b0;
    end
    else if ((addra == 6'd7) && wea && (addrb == 6'd7) && web) begin
        queue_infor_reg_7 <= dina + dinb - queue_infor_reg_7;
    end
    else if ((addra == 6'd7) && wea) begin
        queue_infor_reg_7 <= dina;
    end
    else if((addrb == 6'd7) && web) begin
        queue_infor_reg_7 <= dinb;
    end
    else begin
        queue_infor_reg_7 <= queue_infor_reg_7;
    end
end

always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        queue_infor_reg_8 <= 16'b0;
    end
    else if ((addra == 6'd8) && wea && (addrb == 6'd8) && web) begin
        queue_infor_reg_8 <= dina + dinb - queue_infor_reg_8;
    end
    else if ((addra == 6'd8) && wea) begin
        queue_infor_reg_8 <= dina;
    end
    else if((addrb == 6'd8) && web) begin
        queue_infor_reg_8 <= dinb;
    end
    else begin
        queue_infor_reg_8 <= queue_infor_reg_8;
    end
end

always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        queue_infor_reg_9 <= 16'b0;
    end
    else if ((addra == 6'd9) && wea && (addrb == 6'd9) && web) begin
        queue_infor_reg_9 <= dina + dinb - queue_infor_reg_9;
    end
    else if ((addra == 6'd9) && wea) begin
        queue_infor_reg_9 <= dina;
    end
    else if((addrb == 6'd9) && web) begin
        queue_infor_reg_9 <= dinb;
    end
    else begin
        queue_infor_reg_9 <= queue_infor_reg_9;
    end
end

always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        queue_infor_reg_10 <= 16'b0;
    end
    else if ((addra == 6'd10) && wea && (addrb == 6'd10) && web) begin
        queue_infor_reg_10 <= dina + dinb - queue_infor_reg_10;
    end
    else if ((addra == 6'd10) && wea) begin
        queue_infor_reg_10 <= dina;
    end
    else if((addrb == 6'd10) && web) begin
        queue_infor_reg_10 <= dinb;
    end
    else begin
        queue_infor_reg_10 <= queue_infor_reg_10;
    end
end

always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        queue_infor_reg_11 <= 16'b0;
    end
    else if ((addra == 6'd11) && wea && (addrb == 6'd11) && web) begin
        queue_infor_reg_11 <= dina + dinb - queue_infor_reg_11;
    end
    else if ((addra == 6'd11) && wea) begin
        queue_infor_reg_11 <= dina;
    end
    else if((addrb == 6'd11) && web) begin
        queue_infor_reg_11 <= dinb;
    end
    else begin
        queue_infor_reg_11 <= queue_infor_reg_11;
    end
end

always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        queue_infor_reg_12 <= 16'b0;
    end
    else if ((addra == 6'd12) && wea && (addrb == 6'd12) && web) begin
        queue_infor_reg_12 <= dina + dinb - queue_infor_reg_12;
    end
    else if ((addra == 6'd12) && wea) begin
        queue_infor_reg_12 <= dina;
    end
    else if((addrb == 6'd12) && web) begin
        queue_infor_reg_12 <= dinb;
    end
    else begin
        queue_infor_reg_12 <= queue_infor_reg_12;
    end
end

always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        queue_infor_reg_13 <= 16'b0;
    end
    else if ((addra == 6'd13) && wea && (addrb == 6'd13) && web) begin
        queue_infor_reg_13 <= dina + dinb - queue_infor_reg_13;
    end
    else if ((addra == 6'd13) && wea) begin
        queue_infor_reg_13 <= dina;
    end
    else if((addrb == 6'd13) && web) begin
        queue_infor_reg_13 <= dinb;
    end
    else begin
        queue_infor_reg_13 <= queue_infor_reg_13;
    end
end

always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        queue_infor_reg_14 <= 16'b0;
    end
    else if ((addra == 6'd14) && wea && (addrb == 6'd14) && web) begin
        queue_infor_reg_14 <= dina + dinb - queue_infor_reg_14;
    end
    else if ((addra == 6'd14) && wea) begin
        queue_infor_reg_14 <= dina;
    end
    else if((addrb == 6'd14) && web) begin
        queue_infor_reg_14 <= dinb;
    end
    else begin
        queue_infor_reg_14 <= queue_infor_reg_14;
    end
end

always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        queue_infor_reg_15 <= 16'b0;
    end
    else if ((addra == 6'd15) && wea && (addrb == 6'd15) && web) begin
        queue_infor_reg_15 <= dina + dinb - queue_infor_reg_15;
    end
    else if ((addra == 6'd15) && wea) begin
        queue_infor_reg_15 <= dina;
    end
    else if((addrb == 6'd15) && web) begin
        queue_infor_reg_15 <= dinb;
    end
    else begin
        queue_infor_reg_15 <= queue_infor_reg_15;
    end
end

always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        queue_infor_reg_16 <= 16'b0;
    end
    else if ((addra == 6'd16) && wea && (addrb == 6'd16) && web) begin
        queue_infor_reg_16 <= dina + dinb - queue_infor_reg_16;
    end
    else if ((addra == 6'd16) && wea) begin
        queue_infor_reg_16 <= dina;
    end
    else if((addrb == 6'd16) && web) begin
        queue_infor_reg_16 <= dinb;
    end
    else begin
        queue_infor_reg_16 <= queue_infor_reg_16;
    end
end

always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        queue_infor_reg_17 <= 16'b0;
    end
    else if ((addra == 6'd17) && wea && (addrb == 6'd17) && web) begin
        queue_infor_reg_17 <= dina + dinb - queue_infor_reg_17;
    end
    else if ((addra == 6'd17) && wea) begin
        queue_infor_reg_17 <= dina;
    end
    else if((addrb == 6'd17) && web) begin
        queue_infor_reg_17 <= dinb;
    end
    else begin
        queue_infor_reg_17 <= queue_infor_reg_17;
    end
end

always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        queue_infor_reg_18 <= 16'b0;
    end
    else if ((addra == 6'd18) && wea && (addrb == 6'd18) && web) begin
        queue_infor_reg_18 <= dina + dinb - queue_infor_reg_18;
    end
    else if ((addra == 6'd18) && wea) begin
        queue_infor_reg_18 <= dina;
    end
    else if((addrb == 6'd18) && web) begin
        queue_infor_reg_18 <= dinb;
    end
    else begin
        queue_infor_reg_18 <= queue_infor_reg_18;
    end
end

always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        queue_infor_reg_19 <= 16'b0;
    end
    else if ((addra == 6'd19) && wea && (addrb == 6'd19) && web) begin
        queue_infor_reg_19 <= dina + dinb - queue_infor_reg_19;
    end
    else if ((addra == 6'd19) && wea) begin
        queue_infor_reg_19 <= dina;
    end
    else if((addrb == 6'd19) && web) begin
        queue_infor_reg_19 <= dinb;
    end
    else begin
        queue_infor_reg_19 <= queue_infor_reg_19;
    end
end

always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        queue_infor_reg_20 <= 16'b0;
    end
    else if ((addra == 6'd20) && wea && (addrb == 6'd20) && web) begin
        queue_infor_reg_20 <= dina + dinb - queue_infor_reg_20;
    end
    else if ((addra == 6'd20) && wea) begin
        queue_infor_reg_20 <= dina;
    end
    else if((addrb == 6'd20) && web) begin
        queue_infor_reg_20 <= dinb;
    end
    else begin
        queue_infor_reg_20 <= queue_infor_reg_20;
    end
end

always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        queue_infor_reg_21 <= 16'b0;
    end
    else if ((addra == 6'd21) && wea && (addrb == 6'd21) && web) begin
        queue_infor_reg_21 <= dina + dinb - queue_infor_reg_21;
    end
    else if ((addra == 6'd21) && wea) begin
        queue_infor_reg_21 <= dina;
    end
    else if((addrb == 6'd21) && web) begin
        queue_infor_reg_21 <= dinb;
    end
    else begin
        queue_infor_reg_21 <= queue_infor_reg_21;
    end
end

always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        queue_infor_reg_22 <= 16'b0;
    end
    else if ((addra == 6'd22) && wea && (addrb == 6'd22) && web) begin
        queue_infor_reg_22 <= dina + dinb - queue_infor_reg_22;
    end
    else if ((addra == 6'd22) && wea) begin
        queue_infor_reg_22 <= dina;
    end
    else if((addrb == 6'd22) && web) begin
        queue_infor_reg_22 <= dinb;
    end
    else begin
        queue_infor_reg_22 <= queue_infor_reg_22;
    end
end

always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        queue_infor_reg_23 <= 16'b0;
    end
    else if ((addra == 6'd23) && wea && (addrb == 6'd23) && web) begin
        queue_infor_reg_23 <= dina + dinb - queue_infor_reg_23;
    end
    else if ((addra == 6'd23) && wea) begin
        queue_infor_reg_23 <= dina;
    end
    else if((addrb == 6'd23) && web) begin
        queue_infor_reg_23 <= dinb;
    end
    else begin
        queue_infor_reg_23 <= queue_infor_reg_23;
    end
end

always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        queue_infor_reg_24 <= 16'b0;
    end
    else if ((addra == 6'd24) && wea && (addrb == 6'd24) && web) begin
        queue_infor_reg_24 <= dina + dinb - queue_infor_reg_24;
    end
    else if ((addra == 6'd24) && wea) begin
        queue_infor_reg_24 <= dina;
    end
    else if((addrb == 6'd24) && web) begin
        queue_infor_reg_24 <= dinb;
    end
    else begin
        queue_infor_reg_24 <= queue_infor_reg_24;
    end
end

always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        queue_infor_reg_25 <= 16'b0;
    end
    else if ((addra == 6'd25) && wea && (addrb == 6'd25) && web) begin
        queue_infor_reg_25 <= dina + dinb - queue_infor_reg_25;
    end
    else if ((addra == 6'd25) && wea) begin
        queue_infor_reg_25 <= dina;
    end
    else if((addrb == 6'd25) && web) begin
        queue_infor_reg_25 <= dinb;
    end
    else begin
        queue_infor_reg_25 <= queue_infor_reg_25;
    end
end

always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        queue_infor_reg_26 <= 16'b0;
    end
    else if ((addra == 6'd26) && wea && (addrb == 6'd26) && web) begin
        queue_infor_reg_26 <= dina + dinb - queue_infor_reg_26;
    end
    else if ((addra == 6'd26) && wea) begin
        queue_infor_reg_26 <= dina;
    end
    else if((addrb == 6'd26) && web) begin
        queue_infor_reg_26 <= dinb;
    end
    else begin
        queue_infor_reg_26 <= queue_infor_reg_26;
    end
end

always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        queue_infor_reg_27 <= 16'b0;
    end
    else if ((addra == 6'd27) && wea && (addrb == 6'd27) && web) begin
        queue_infor_reg_27 <= dina + dinb - queue_infor_reg_27;
    end
    else if ((addra == 6'd27) && wea) begin
        queue_infor_reg_27 <= dina;
    end
    else if((addrb == 6'd27) && web) begin
        queue_infor_reg_27 <= dinb;
    end
    else begin
        queue_infor_reg_27 <= queue_infor_reg_27;
    end
end

always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        queue_infor_reg_28 <= 16'b0;
    end
    else if ((addra == 6'd28) && wea && (addrb == 6'd28) && web) begin
        queue_infor_reg_28 <= dina + dinb - queue_infor_reg_28;
    end
    else if ((addra == 6'd28) && wea) begin
        queue_infor_reg_28 <= dina;
    end
    else if((addrb == 6'd28) && web) begin
        queue_infor_reg_28 <= dinb;
    end
    else begin
        queue_infor_reg_28 <= queue_infor_reg_28;
    end
end

always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        queue_infor_reg_29 <= 16'b0;
    end
    else if ((addra == 6'd29) && wea && (addrb == 6'd29) && web) begin
        queue_infor_reg_29 <= dina + dinb - queue_infor_reg_29;
    end
    else if ((addra == 6'd29) && wea) begin
        queue_infor_reg_29 <= dina;
    end
    else if((addrb == 6'd29) && web) begin
        queue_infor_reg_29 <= dinb;
    end
    else begin
        queue_infor_reg_29 <= queue_infor_reg_29;
    end
end

always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        queue_infor_reg_30 <= 16'b0;
    end
    else if ((addra == 6'd30) && wea && (addrb == 6'd30) && web) begin
        queue_infor_reg_30 <= dina + dinb - queue_infor_reg_30;
    end
    else if ((addra == 6'd30) && wea) begin
        queue_infor_reg_30 <= dina;
    end
    else if((addrb == 6'd30) && web) begin
        queue_infor_reg_30 <= dinb;
    end
    else begin
        queue_infor_reg_30 <= queue_infor_reg_30;
    end
end

always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        queue_infor_reg_31 <= 16'b0;
    end
    else if ((addra == 6'd31) && wea && (addrb == 6'd31) && web) begin
        queue_infor_reg_31 <= dina + dinb - queue_infor_reg_31;
    end
    else if ((addra == 6'd31) && wea) begin
        queue_infor_reg_31 <= dina;
    end
    else if((addrb == 6'd31) && web) begin
        queue_infor_reg_31 <= dinb;
    end
    else begin
        queue_infor_reg_31 <= queue_infor_reg_31;
    end
end

always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        queue_infor_reg_32 <= 16'b0;
    end
    else if ((addra == 6'd32) && wea && (addrb == 6'd32) && web) begin
        queue_infor_reg_32 <= dina + dinb - queue_infor_reg_32;
    end
    else if ((addra == 6'd32) && wea) begin
        queue_infor_reg_32 <= dina;
    end
    else if((addrb == 6'd32) && web) begin
        queue_infor_reg_32 <= dinb;
    end
    else begin
        queue_infor_reg_32 <= queue_infor_reg_32;
    end
end

endmodule